The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely sophisticated devices, and computer systems may be found in many different settings. Computer systems typically include a combination of hardware (such as semiconductors, integrated circuits, programmable logic devices, programmable gate arrays, and circuit boards) and software, also known as computer programs.
The typical design methodology for integrated circuit designs—such as very large scale integrated (VLSI) circuits and application specific integrated circuits (ASICs)—is conventionally divided into the following three stages: first a design capture step is performed using, for example, a high level language synthesis package. Next, design verification is made on the resulting design. This includes simulations, timing analysis, and automatic test pattern generation (ATPG) tools. Finally, there is layout and eventual tape out of the device. The device is then tested, and the process may need to be reiterated one or more times until the desired design criteria are satisfied.
Currently, electronic design automation (EDA) tools are used to define and verify prototype systems. Conventional EDA tools provide computer-aided facilities for electronic engineers to define prototype designs, typically by generating either netlist files, which specify components and their interconnections, or hardware description files, which specify prototype system functionality according to a hardware description language (HDL).
Initially, the desired functionality for a circuit is analyzed by one or more designers. They define the logical components of the circuit and their interactions by specifying the logic design using design capture tools.
Two common methods for specifying the design are schematic capture and hardware description languages. Both of these methods allow a circuit designer to specify the circuit at the register transfer level. The schematic capture method provides a user interface, which allows a logic circuit to be drawn in graphical form on a computer display. Using this method, the circuit is defined as small building blocks, which can be used to develop higher level designs with increasing degrees of abstraction.
Encoding the design in a hardware description language (HDL) is the other major design entry technique used to specify modern integrated circuits. Hardware description languages are specially developed to aid a designer in describing a circuit. The HDL program specifying the design may be compiled into the same data format produced by schematic capture. This capability provides the designer great flexibility in methods used for specifying a logic design.
Next, it is necessary to verify that the logic definition is correct and that the circuit implements the function expected by the designers. Typically, this involves timing analysis and simulation tools. The data representation in the logic design database may be reformatted as needed prior to use by the timing analysis and simulation tools. The design undergoes design verification analysis in order to detect flaws in the design. The design is also analyzed by simulating the device resulting from the design to assess the functionality of the design. If errors are found or the resulting functionality is unacceptable, the designer modifies the design as needed. These design iterations help to ensure that the design satisfies its requirements.
Other verification methods include generating software models of the logic circuit design and testing the software model of the design with designer-specified test cases. Because it is not possible to check every possible condition that may be generated in the actual logic design, faulty logic may remain because it would not have been exercised by any of the test cases. Errors in the logic design may remain undetected until the release of a product on the marketplace, where it may cause costly redesigns.
Formal verification is another way to check logic design prior to the fabrication of a device. Formal verification is a technique wherein a logic circuit is modeled as a state transition system, and specifications are provided for components in the system. One way in which specifications may be made is through the use of logic formulas. Each of the components in the logic design is specified, and all possible behaviors of the design may be exercised by a tool which confirms that these specifications are met.
Once a netlist has been generated from the logic design, there are a number of commercially available silicon compilers, also called place and route tools, which are used to convert the netlist into a semiconductor circuit layout. The semiconductor circuit layout specifies the physical implementation of the circuit in silicon or other semiconductor materials.
As can be seen from the description above, the design verification step can be quite complicated and resource intensive. This complicated nature of design verification is exacerbated when a computer system contains hundreds of I/O (Input/Output) models that need to be characterized for simulation.
What is needed is a better way to handle the many I/O models that must be characterized for simulation.